Embodiments of the present disclosure generally relate to issuing instructions in a processor, and more specifically, to techniques for back-to-back issue of instructions in the processor.
A conventional superscalar processor may issue instructions out-of-order with respect to a predefined program order. Because subsequent instructions are often dependent upon results of previous instructions, an issue queue in the processor may use a dependency tracking scheme to ensure that all data dependencies are followed. For instance, in one approach, the processor includes an age array that tracks a relative age of instructions managed in the issue queue. The age array allows an instruction select logic to select an oldest ready entry in the issue queue for issue to an execution unit of the processor.
Issuing a given instruction from the issue queue may resolve outstanding operand dependencies for other instructions stored in the issue queue. In a current approach, the processor compares an instruction tag of a producer instruction selected for issue against source instruction tags of the instructions stored in the issue queue. The processor does so to identify dependent instructions to wake up (i.e., indicate to a given dependent instruction that source operands are available for that instruction) for possible issue in a next cycle. For optimal issue bandwidth, it is preferable to issue such instructions in the cycle immediately following the issue of the producer instruction. However, this approach creates a timing critical path due to the instruction tag comparisons after the producer instruction has been selected for issue.